DFB FIR Filter -

// Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
// Filter coefficients are stored in RAM-B
area acu
  // 16 taps
  dw 0x0F0F // mreg
  dw 0x0000 // lreg
  dw 0x0000 // initial value for ACU-A.reg
  
area data_b
  // 16 taps
  dw 0x00E168
  dw 0x00432A
  // add another 14 taps here...
 
initial:
  // Enable modulus arithmetic
  acu(setmod,setmod) dmux(sa,sa) alu(set0) mac(clra)  
  acu(clear,clear) dmux(sa,sa) alu(hold) mac(hold) jmp(eob, wait_for_data)

wait_for_data:
  // Wait input from stage-A(in1) for the next element
  acu(hold,hold) dmux(sa,sa) alu(hold) mac(hold) jmpl(in1,load_data)    

load_data:
  // Load (mreg,lreg) with (acu[0],acu[1])
  acu(loadm,loadm) addr(0) dmux(sa,sa) alu(hold) mac(hold)                   
  acu(loadl,loadl) addr(1) dmux(sa,sa) alu(hold) mac(hold)
  // Open the channel from stage-A(addr(1)) to RAM-A at mux1a
  acu(hold,hold) addr(1) dmux(ba,sa) alu(hold) mac(hold)      
  // Write data to RAM-A, modify mux, load acu-A with acu[2]
  acu(read,clear) addr(2) dmux(sra,sra) alu(setb) mac(clra) write(da) jmp(eob, calc)
  
write_bus:
  // Write acu[2] with acu-A.reg  
  acu(write,clear) addr(2) dmux(sa,srm) alu(setb) mac(hold)
  acu(hold,hold) dmux(sa,sa) alu(hold) mac(hold)
  // Write shifter output to the bus' holding register A with addr(1)
  acu(hold,hold) addr(1) dmux(sa,sa) alu(hold) mac(hold) write(abus) jmp(eob, wait_for_data)

calc:
  // Multiplication
  acu(incr,incr) dmux(sra,srm) alu(setb) mac(macc) jmpl(eob, acubeq, write_bus)    

32 bit Shift Register with DMA

1. Setup the Status Registers

Using Status Register to create a 32 bit shift register.  It requires four status registers with a 32 bit aligned address.  Using sticky mode to sync the data with a signal.

Using Directives to force the four status register into the right UDBs.

Component Name: \Status_Reg_1:sts:sts_reg\
Directive Type: ForceComponentUDB
Directive Value: U(1,1)

the Directive Values for the other three are U(0,1),U(0,0),U(1,0).

the UDB status registers are B1_UDB08_ST, B1_UDB09_ST, B1_UDB10_ST, B1_UDB11_ST

2. Setup the DMAs

Using two DMAs to do the work.  The first DMA will copy the values in the four status registers to a temporary 32bit data buffer one by one in one request.  After it's done, it triggers the 2nd DMA to copy the temporary data to the 32 bit data array.  Please check AN61102 20-Bit ADC Data Buffering Using DMA for the detail explanation.

> the 1st DMA setup:
BYTES_PER_BURST   4
REQUEST_PER_BURST 1
TRANSFER_COUNT    4

configuration: TD_TERMOUT_EN | TD_INC_SRC_ADR | TD_INC_DST_ADR

> the 2nd DMA setup:
BYTES_PER_BURST   4
REQUEST_PER_BURST 1

configuration: TD_INC_DST_ADR

16 bit access mode: using B1_UDB08_09_ST

SIO - Vref

We can have different Vddio for different IO blocks.  But in some dev kits, the Vddio might be tied to the Vdd.  If we want to have a different voltage level for the IO pins, we can try using the SIO pins.

We can use DAC to generate the required voltage level and use OpAmp to give a proper current source.

Shift Register - Interrupt Testing (On Store)

The interrupt on component Shift Register is fired when there is a store signal activated.

Clear the interrupt by reading the interrupt status register or by calling ShiftReg_#_GetIntStatus();

The interrupt signal will also be updated when FIFO is updated, for example, after calling ShiftReg_#_ReadRegValue();  This will change the status register.

A simple test can be done by wiring the signal to an output LED...